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http://portal.acm.org/citation.cfm?id=1515833 “This paper presents a new set of techniques for hard-ware implementations of Secure Hash Algorithm (SHA) hash functions. These techniques consist mostly in operation rescheduling and hardware reutilization, therefore, significantly decreasing the critical path and required area. Throughputs from 1.3 Gbit/s to 1.8 Gbit/s were obtained for the SHA implementations on a Xilinx VIRTEX II Pro. ”

http://www.hitechglobal.com/xilinx/ml361.htm ML361 - Xilinx Virtex-II Pro DDR 400/PC3200 Memory Board $2,500

bitcoin/fpga.txt · Last modified: 2016/06/25 11:25 (external edit)